View AT90SP0801-01SC_2366665.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

note: this is a summary document. a complete document is available under nda. for more information, please contact your local atmel sales office. features ? secure computation of public key signatures secure storage and decryption of symmetric keys on-chip cache for frequently used keys smbus communications port on-board public key computation engine and microprocessor physical and logical security measures to inhibit attacks 20-lead soic package, 0 c to +70 c operating range 3.3v 10% supply voltage description the at90sp0801 is used to perform cryptographic operations, using asymmetric pri- vate keys stored in its internal eeprom. an arbitrary number of private keys can be stored externally and decrypted by the chip when required. communication to the sys- tem processor is via the smbus. figure 1. pin configuration name description reset reset input, active-low scl smbus clock sda smbus data gnd ground clkin input clock vcc operating voltage test do not connect 1 2 3 4 5 6 7 8 9 10 11 12 13 14 reset nc nc nc nc nc scl sda nc nc nc gnd nc nc 28 27 26 25 24 23 22 21 20 19 18 17 16 15 nc nc vcc nc nc nc nc nc clkin test test nc nc nc 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 reset nc nc nc nc scl sda nc nc gnd vcc nc nc nc nc clkin test nc nc test 28-lead tssop 28-lead soic secure signature generation chip at90sp0801 summary rev. 1495as?01/02
2 at90sp0801 1495as?01/02 figure 2. block diagram i/o buffer 8/16-bit avr p program memory crypto data buffer public key crypto engine hardware key private key password eeprom registers user key buffer 0 private key password, mode crc tag user key buffer 1 private key password, mode crc tag other configuration registers: lock, status error, vers failcnt, config commands data smbus control: data: clkin reset key:
3 at90sp0801 1495as ? 01/02 serial interface data is transferred to or from the i/o buffer on the chip using the smbus interface, in a manner similar but not identical to that of standard two-wire serial eeproms. all bits are sent to or read from the chip most significant bit first, in a manner consistent with standard serial eeproms. bit fields listed in this document are correspondingly listed with the msb on the left and the lsb on the right. hex numbers are specified with the ? 0x ? prefix. multi-byte information sent to the chip is sent most significant byte first, following typical conventions. within the chip, the first byte sent to the chip is stored in memory at the lowest address, and the address is incremented for subsequent bytes. when a mes- sage digest (hash) is sent to the chip, the first byte of the hash value is the first byte to be sent to the chip. in both the text and graphics, the chip is the slave and the system is the master. the fol- lowing abbreviations apply: for the graphical representations, the direction of the data flow is indicated as below: smbus standard usage data transfer to and from the chip follows the smbus v1.1 standard, using only some of the command protocols. the ? write ? command of this chip uses the ? block write ? protocol of the smbus spec. note that in this chip the count value can exceed 32. this chip does not support the ? write byte ? and ? write word ? protocols of the smbus spec. the ? read ? command of this chip uses the ? block read ? protocol of the smbus spec. note that in this chip the ? read ? command can be optionally executed without the pre- ceding partial block write command. this chip does not support the ? receive byte ? , ? read byte ? and ? read word ? protocols of the smbus spec. all other commands of this chip use the ? send byte ? protocol of the smbus spec. note that the ? quick command ? and ? process call ? protocols of the smbus spec are not sup- ported by this chip. two-wire serial eeprom comparison some of the differences between this chip and a standard two-wire serial eeprom are: 1. the slave address of this chip is different from the a0-af (hex) standard for eeproms. 2. the maximum clock rate is 100 khz and tdh is 300 ns. these specs are part of smbus. 3. the supply voltage is 3.0v to 3.7v. 4. the read address is not specified in the aborted read command. 5. multi-byte reads and writes are preceded by the number of bytes that will be transferred. a acknowledge (bus pulled low, master or slave) n not acknowledge (bus left high, master or slave) s start (high-to-low on sda with scl high, master) p stop (low-to-high on sda with scl high, master) slave to master (chip to system) master to slave (system to chip)
4 at90sp0801 1495as ? 01/02 6. multi-byte writes longer than the maximum size of the register (i.e., containing more bytes) cause an error. commands without data transfer there are a number of commands (described within the following commands sections) that perform various internal operations on the chip, using data already stored in either the i/o buffer or the internal memories of the chip. all such commands are composed of two bytes sent to the chip according to the following flow: write commands the write commands permit data to be transferred to the i/o buffer located within the sram on the chip. only block writes are supported, so transfers of 1 or 2 bytes require the same basic sequence as 32 bytes. the commands are encoded as follows: the following figure shows the structure for block write operations: the write buffer command is followed by up to 255 bytes of data. all bytes are sourced by the host and are formatted as follows: count denotes the total number of bytes that follows the command, including any crc bytes. a 0 value is illegal. 255 is the max. number of bytes that may be written per command. s slave address wr a command code ap start condition r/w bit acknowledge stop condition 1 7 1 1 8 11 number of bits slave address command code description 01010000 s 1 s 0 000000 write buffer, (+data) 01010010 01111111 write command, ignored 01010000 01111111 write command, ignored 17 11 8 1 ... s slave address wr a command code a 81 8 181 ... 811 byte count = n a data byte 1 a data byte 2 a data byte n a p 01010000 s 1 s 0 000000 count data0 data1 ? datan crc0 crc1
5 at90sp0801 1495as ? 01/02 data is sent least significant byte first. in some circumstances, there may be no data , only crc . depending on the value of ss, the crc bytes may or may not be included. the two sequence bits s 1-0 within the command code tell the chip how to relate this transfer to previous and subsequent transfers. s 0 if set to a 1 indicates that this is the first transfer to the buffer and that data0 should go into buffer address 0 and so on. if this bit is set to a 0, then data0 will be stored in the next location within the buffer after that from the previous transfer. when set, this bit also resets the crc generator. s 1 if set to a 1 indicates that this is the last transfer to the buffer. if set to a 0, the chip must have previously executed a command where s 0 was set to a 1. when s 1 is set to a 1, the last two bytes of the information transferred in this block are a crc value. the chip will nack the crc1 byte, if the value sent does not match that computed on the incoming data. the crc bytes may not be split across two blocks. for instance, to write password information (64 bytes) to the chip, the following sequence of three write commands would be used (assuming 32 byte loads). the acks, nacks and stop conditions have been ignored for clarity. for shorter data transfer values, it is perfectly legal for both s 0 and s 1 to be set. this indi- cates that the entire transfer is taking place in a single block access. as an example of this, the following command would write a single byte to the buffer: the chip will nack writes that attempt to write into the chip beyond the internal buffer, which may be as short as 320 bytes. s 01010000 01000000 00100000 data0 data1 data2 ... data31 s 01010000 00000000 00100000 data32 data33 data34 ... data63 s 01010000 10000000 00000010 crc0 crc1 s 01010000 11000000 00000011 data0 crc0 crc1
6 at90sp0801 1495as ? 01/02 read commands block read commands are slightly different than writes and are encoded as follows: the read command is only one byte long, and the chip (not the host) sends back the count information. the count value will always be the smaller of maxblk_r or the (remaining) number of bytes in the register that have not been read yet. when there are a large number of bytes in the buffer, multiple read commands must be executed to read all the bytes out of the chip. using the slave address of 0x53 will cause the chip to start reading at the beginning of the buffer. using the slave address of 0x51 will cause the chip to continue reading information that is subsequent to the information last read by the chip from the buffer. after a load or crypto operation, the first command may also be a 0x51, which will have the same effect as 0x53. block reads are formatted as follows: after the last byte has been read from the register, the read pointer is reset back to the beginning of the register, and the system may continue to read from the beginning of the buffer again, if desired. there is no indication from the chip as to when the read pointer has been reset (other than as may be inferred from the values in the count field). to be compatible with the smbus specification, the read command may optionally be preceded by the first two bytes of either of the ? ignored write ? commands, which are then aborted with a new start bit for the read. the two bytes of the write command are com- pletely ignored by the chip in this case, and a different encoding for the second byte (01111111, or 0x7f) must be used. execution of a block read sequence using a legal write command code for the second byte (00, 0x40, 0x80 or 0xc) is undefined. the protocol for this is shown below: slave address command code description 01010011 -------- read buffer, first block 01010001 -------- read, subsequent blk 17 11 8 1 ... s slave address rd a byte count = n a 8181 ... 811 data byte 1 a data byte 2 a data byte n np 17 11811 7 11 ... s slave address wr a 0111 1111 as slave address rd a 818181 ... 811 byte count = n a data byte 1 a data byte 2 a data byte n np
7 at90sp0801 1495as ? 01/02 as an example of the read block command, the following would take place to read four bytes of data from the buffer (assuming that the load vers_r command had previously been executed). or as an example of multiple read block command, the following would take place to read the 1040 bits (130 bytes) of signature data from the buffer (assuming that the ? sign ? command had previously been executed). as earlier, the two-byte aborted write is an option on each command. note that the first byte read (data0) is the most significant byte of the signature, while data128 is the most significant byte of the crc. s 01010011 00000100 data0 data1 data2 data3 s 01010010 01111111 s 01010011 00000100 data0 data1 data2 data3 s 01010010 01111111 s 01010011 00100000 data0 data1 ... data31 s 01010000 01111111 s 01010001 00100000 data32 data33 ... data63 s 01010000 01111111 s 01010001 00100000 data64 data65 ... data95 s 01010000 01111111 s 01010001 00100000 data96 data97 ... data127 s 01010000 01111111 s 01010001 00000010 data128 data129 ...
8 at90sp0801 1495as ? 01/02 serial interface ac specifications figure 3. timing diagram for serial interface ac specification absolute maximum ratings operating temperature...................................0 c to +70 c storage temperature (without bias)................0 c to +70 c *notice: stresses beyond those listed under ? absolute maximum ratings ? may cause permanent dam- age to the device. this is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification may cause temporary or permanent failure. exposure to absolute maximum rating conditions for extended periods may affect device reliability. votage on i/o pins..................................-0.1 to v cc +0.3v voltage on vcc with respect to ground......................6.0v maximum esd voltage..............................................2000v c l = 1 ttl gate and 100 pf, except as noted. v cc = 3.0v to 3.7v. name min max units notes t scl 100 khz clock (scl) frequency t low 4.7 s clock (scl) pulse low-width t high 4.0 s clock (scl) pulse high-width t i 100 ns noise suppression, not tested t aa 0.1 4.5 s clock low to data out valid t buf 4.7 s bus free before transmission, not tested t hd.sta 4.0 s start hold time t su.sta 4.7 s start set-up time t hd.dat 0 s data in hold time t su.dat 200 ns data in set-up time t r 1.0 s inputs rise time, not tested t f 300 ns inputs fall time, not tested t su.sto 4.7 s stop set-up time t dh 300 ns data out hold time t wr 10 ms write cycle time, eeprom write t clkin 69 100 ns clkin period t clko , t ckh1 34 50 ns clkin low or clkin high
9 at90sp0801 1495as ? 01/02 serial interface dc specifications notes: 1. the specifications noted as ? not tested ? denote parameters that are characterized and not 100% tested. 2. preliminary data, subject to change. operating temperature range = 0 to 70 c. name min typ max units notes v cc 3.0 3.7 v operating voltage, v cc pin i cc (1) 18 25 ma at v cc = 3.7v, f sda = 100 khz i sb (1) 50 100 a at v cc = 3.3v, clkin = v ss i lio 0.1 3.0 a sda, scl. v in = v cc or v ss v il ? 0.1 v cc x 0.3 v v ih v cc x 0.7 v cc v v ol 0.4 v i ol = 2.1 ma c io pf scl, sda, not tested f clkin 1 14.318 15 mhz duty cycle >48% and <52%
10 at90sp0801 1495as ? 01/02 ordering information ordering code package operation range AT90SP0801-01SC 20s, 20-lead soic commercial (0 c to 70 c) package type 20s 20-lead, 0.300 wide, plastic gull wing small outline (soic)
packaging information 11 at90sp0801 1495as ? 01/02 0.299 (7.60) 0.291 (7.39) 0.020 (0.508) 0.013 (0.330) 0.420 (10.7) 0.393 (9.98) pin 1 .050 (1.27) bsc 0.513 (13.0) 0.497 (12.6) 0.012 (0.305) 0.003 (0.076) 0.105 (2.67) 0.092 (2.34) 0 8 ref 0.035 (0.889) 0.015 (0.381) 0.013 (0.330) 0.009 (0.229) .224" (6.2) .236" (6.0) .319" (8.1) bsc .0075" (0.19) .0118" (0.30) .002" (0.05) .006" (0.15) .386"(9.8) .043" (1.10) max .378"(9.6) .030" (0.75) .0079" (0.20) ref 0? 8? .020" (0.50) .0035" (0.09) .026" (0.65) bsc 20s , 20 lead, 0.300" wide, plastic gull wing small outline (soic) dimensions in inches and (millimeters) 28a , 28-lead, 6.1mm wide, thin shrink small outline package (tssop) dimensions in inches and (millimeters)
printed on recycled paper. ? atmel corporation 2002. atmel corporation makes no warranty for the use of its products, other than those expressly contained in the companys standard warranty which is detailed in atmels terms and conditions located on the companys web site. the company assumes no responsibility for any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without n otice, and does not make any commitment to update the information contained herein. no licenses to patents or other intellectual property of at mel are granted by the company in connection with the sale of atmel products, expressly or by implication. atmels products are not authorized for use as critical components in life support devices or systems. atmel headquarters atmel operations corporate headquarters 2325 orchard parkway san jose, ca 95131 tel 1(408) 441-0311 fax 1(408) 487-2600 europe atmel sarl route des arsenaux 41 casa postale 80 ch-1705 fribourg switzerland tel (41) 26-426-5555 fax (41) 26-426-5500 asia atmel asia, ltd. room 1219 chinachem golden plaza 77 mody road tsimhatsui east kowloon hong kong tel (852) 2721-9778 fax (852) 2722-1369 japan atmel japan k.k. 9f, tonetsu shinkawa bldg. 1-24-8 shinkawa chuo-ku, tokyo 104-0033 japan tel (81) 3-3523-3551 fax (81) 3-3523-7581 memory atmel corporate 2325 orchard parkway san jose, ca 95131 tel 1(408) 436-4270 fax 1(408) 436-4314 microcontrollers atmel corporate 2325 orchard parkway san jose, ca 95131 tel 1(408) 436-4270 fax 1(408) 436-4314 atmel nantes la chantrerie bp 70602 44306 nantes cedex 3, france tel (33) 2-40-18-18-18 fax (33) 2-40-18-19-60 asic/assp/smart cards atmel rousset zone industrielle 13106 rousset cedex, france tel (33) 4-42-53-60-00 fax (33) 4-42-53-60-01 atmel colorado springs 1150 east cheyenne mtn. blvd. colorado springs, co 80906 tel 1(719) 576-3300 fax 1(719) 540-1759 atmel smart card ics scottish enterprise technology park maxwell building east kilbride g75 0qr, scotland tel (44) 1355-803-000 fax (44) 1355-242-743 rf/automotive atmel heilbronn theresienstrasse 2 postfach 3535 74025 heilbronn, germany tel (49) 71-31-67-0 fax (49) 71-31-67-2340 atmel colorado springs 1150 east cheyenne mtn. blvd. colorado springs, co 80906 tel 1(719) 576-3300 fax 1(719) 540-1759 biometrics/imaging/hi-rel mpu/ high speed converters/rf datacom atmel grenoble avenue de rochepleine bp 123 38521 saint-egreve cedex, france tel (33) 4-76-58-30-00 fax (33) 4-76-58-34-80 e-mail literature@atmel.com web site http://www.atmel.com at m e l isthe registered trademarks of atmel. 1495as01/02/xm

▲Up To Search▲

Price & Availability of AT90SP0801-01SC

	To Download AT90SP0801-01SC Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .